EasyECO utilizes standard cells, spare cells (including filler cells and gate array), and replaced standard cells to construct patch circuit, and optimizes the patch for better timing results based on the physical information of the spare cells provided by the user.

Input files:

   1) RTL design

   2) Gate-level netlist (Verilog)

   3) Standard cell library (Liberty)

Required input files according to specific the design requirements:

   1) SVF or VSDC file

   2) Physical design files (DEF, LEF)

EasyECO output files:

   1) A netlist that satisfies the ECO function

   2) Third-party tool scripts that perform the ECO function downstream

EasyECO offers significant advantages over traditional ECO solutions, including a highly efficient algorithm that improves the utilization of spare resources and speeds up total operations. 

Notably, EasyECO enables a significantly larger scale of functional ECO, providing a new level of capability to the ASIC design community. Test results indicate that EasyECO requires on average 30% fewer instance resources compared to traditional solutions, with some cases achieving a reduction of 10 times or more. Tool run time is also over 10 times faster, with speed improvement increasing as the design scale grows larger.