Yes.  Test circuitry such as scan chains and MBIST should not be affected during the ECO process. EasylogicECO generates SDFF(s) and adds the SDFF(s) to the scan chains based on the needs of the new netlist.

To learn more, please refer to the AppNote "Performing Scan Chain Fixing during Functional ECO Process" under the Resources section.

Yes, EasylogicECO utilizes a unique reverse engineering analysis technology to identify signals that were removed during RTL synthesis from the gate-level netlist. This enables the selection of the optimal ECO point, ensuring successful completion of the ECO task.

EasylogicECO helps design teams complete ECO tasks in the shortest turnaround time, avoiding delays in the design cycle.

EasylogicECO uses a breakthrough RTL-based Functional ECO algorithm to effectively perform automatic operations that generate minimal logic changes on the netlist to ensure that the modified netlist is consistent with the revised RTL function.

To learn more, please refer to the white paper "RTL-Based Full-Module Functional ECO Methodology" under the Resources section of our website

EasylogicECO automatically modifies the corresponding gate-level netlist according to designer’s functional changes of the RTL code, so the modified gate-level netlist has the same function as the modified RTL code.   

EasylogicECO changes the connections of standard cells of the gate-level netlist, adding new cells or deleting old cells, and finds the minimum scale of logic change.

To learn more, please refer to the white paper "RTL-Based Full-Module Functional ECO Methodology" under the Resources section of our website.

EasyECO considers the characteristics, and design requirements, of advanced processes 10nm and below and performs additional logic and physical optimizations.

Yes, EasylogicECO results are optimized for shortest paths.  Instead of calculating the delay of each cell unit, EasylogicECO selects appropriate patch logic based on logic level, the most appropriate spare units based on their physical locations, and clock signals from the clock tree for each generated test register based on the required scan chain function.

To learn more, please refer to the white paper "RTL-Based Full-Module Functional ECO Methodology" under the Resources section of our website.