This process focuses on implementing connectivity changes using the metal layers of the chip. Metal-only ECO and patch logic creation are tightly integrated, as the physical ECO resources available near the patch location directly influence the patch creation process. Metal-Only ECO allows modifications without altering the base layers, enabling faster turnaround and lower manufacturing costs while ensuring compatibility with the existing design.
EasylogicECO's patented physical-aware ECO algorithm streamlines multiple aspects of the metal-only ECO process into a single flow. The algorithm evaluates:
1. The location of the ECO point
2. Path delay
3. Spare resources near the ECO poin
4. Congestion analysis
5. Wire delay introduced by the routing distance
6. Constraint file output for the subsequent P&R run
as part of the patch logic creation process. With a focus on total ECO efficiency, the algorithm automates iterations among combinations of ECO points and patch results to deliver the shortest possible ECO turnaround.
Physical-aware ECO algorithm leverages the user's LEF/DEF information of the existing netlist and spare resources. The usable spare resources include:
1. Spare gates
2. Gate arrays
3. Configurable filler cells
4. Standard cells disengaged from the original netlist.
The ECO operation performs a trade-off between spare cell function and the path delay caused by both the instances and the wiring length to ensure the path delay meet the original requirement.
Automated iteration process for identifying optimal ECO points, minimizing patch logic, and optimizing path delay, significantly increases the success rate of metal-only ECO tasks.
Metal-Only ECO operations encompass the use of two distinct types of tool features: physical resource-based implementation optimizations and patch logic creation results derived from RTL changes. This section focuses on the physical implementation features.
Physical-Aware Logic Optimization Strategy
This capability provides a powerful delay estimation strategy for logic optimization in the ECO process. By utilizing the LEF/DEF files of the original gate-level netlist, it calculates delay estimates based on target cell types and physical locations. This enables more accurate delay optimization, taking into account the layout and physical characteristics of the design. One notable advantage of this capability is that it does not impose limitations on the available cell functions for ECO, making it highly flexible and adaptable to various design scenarios.
Optimization Based on Available Resources in the Vicinity
This capability optimizes the logic function, gate type, and location of available gates by leveraging the resources in the vicinity of the ECO point. It takes into account the layout constraints, such as LEF and DEF inputs, to optimize the design based on the available resources, resulting in more efficient and optimized placement of gates.
User-Specified Gate Regions
Users have the flexibility to define specific areas in the ECO process to further improve the logic optimization results. This includes the ability to define prioritized or restricted regions, allowing users to customize the ECO process based on their design requirements or constraints.
Types of Supported Physical Resources
This capability supports various cell types of spare resources, including spare cell instances, gate arrays, configurable filler cells, and the disengaged standard cells from the original netlist. This wide range of supported cell types provides users with ample flexibility to choose the resources for their specific design needs.
APR Flow Support
This capability generates layout instructions in both TCL and netlist formats, specifically tailored for APR (Automatic Place and Route) tools, which can be easily integrated into users' preferred APR tool of choice. This streamlines the ECO process and simplifies the generation of optimized layout instructions, making it more efficient and user-friendly.
