SDFF selection and conversion
Converts regular DFFs in the logic patch into appropriate SDFFs that need to be inserted into the scan chain.
Scan chain stitching, removal and balancing
Stitches SDFFs into the original scan chain while disconnecting unnecessary SDFFs. Customizes the chain length based on user’s DFT constraints to meet the requirements of the test plan, enabling increased test coverage without compromising testing costs.
Support for advanced design requirements
Ensures compliance with design rules while implementing scan chain revisions. Identifies multi-clock domains, multi-power domains, and hold time violations and applies necessary adjustments, such as isolation/level shifter cells or lockup latches.
Physical-aware metal-only ECO algorithm
Utilizes physical information provided in the LEF/DEF format to enhance timing of the scan chain. Resource options for a post-layout ECO task include spare cells, gate arrays, and filler cells. When combined with physical information, optimizes the delay of scan chains by considering cell function and estimated wire delay.
Versatile design flow support
Supports various ECO flows for introducing changes of FFs, including EasylogicECO flow, 3rd-party ECO flow, and manual ECO flow. It utilizes standard formats for input/output data, enabling seamless integration with mainstream ASIC design flow.
Command line script operations
Script-based operation is simple, easy to learn and debug. It only requires modifying specific script fields when migrating to other projects.