A functional ECO tool modifies the logic function of the chip netlist at a late stage in the design process—usually after place and route (P&R), when the layout is completed, or sometimes even after masking. Its purpose is to reconnect a small portion of the gates to match the updated functionality using metal routing layers.

Changing logic functionality by adding a netlist patch to the existing netlist can save significant project time. When an ASIC design project reaches the post-layout stage, resynthesizing the netlist from revised RTL to incorporate new logic functions—and subsequently repeating the entire ASIC design flow—can be extremely time-consuming and may jeopardize the entire project.

Application scenarios include adding new features, or fixing design errors, and improving chip performance, whenever it is necessary to change the logic function of the chip design.

Functional ECO can be applied at any phase of the design process, even after tape-out. However, the implementation of ECOs varies depending on the stage. Before layout completion, there are generally no strict limitations on available resources. After layout is finalized, only the spare resources reserved for ECO can be utilized. Additionally, since the number of spare resources is limited, the scale of functional changes is also constrained.