A patch logic generation process involves the work between the RTL specification changes and the generation of the logic patch.
This process focuses on identifying the nets and gates that can be replaced with the minimum number of new gates that, in turn, generate the equivalent function of the revised RTL.
The details related to this process are provided below.
Time-to-market pressure
The Easylogic solution leverages a unique algorithm to meticulously trace the original netlist, enabling the identification of optimal ECO points for efficient design modifications. It also employs specialized optimization algorithms designed to adapt seamlessly to a wide range of designs, ensuring robust and reliable performance across different scenarios.
Furthermore, the solution provides extensive constraint options, allowing users to specify various design requirements with precision. This combination of innovative tracing, optimization capabilities, and customizable constraints ensures that Easylogic delivers tailored and high-quality results for complex ECO challenges.
The total ECO turnaround time is determined by several key factors: design preparation time, tool runtime, downstream P&R runtime, and result verification time. The Easylogic solution is specifically engineered to efficiently handle design sizes of up to 5 million instances with minimal impact on tool runtime.
Additionally, its ability to generate compact, physical-aware patches significantly accelerates the downstream P&R process, enabling swift completion. This comprehensive approach ensures that each stage of the ECO flow is optimized for both speed and scalability, ultimately reducing overall turnaround time.
EasylogicECO's patented algorithm eliminates the need for users to painstakingly trace the gate-level netlist in an attempt to identify ECO points, even when RTL signals have been optimized out, the netlist has been flattened, the change is instantiated multiple times, or the modified function spans across different design hierarchies.
Its highly automated flow requires minimal design knowledge from the user and ensures efficient, accurate results without the need for extensive manual intervention.
RTL-based ECO design flow
The ECO flow begins with a functional comparison between the revised RTL code and the original RTL, ensuring that the differences accurately capture the genuine intent of the user's functional change. EasylogicECO does not use netlist-to-netlist comparison to capture functional changes, as it typically results in false ECO requirements.
It is recommended to use the full system module as the input circuit, as it eliminates the need for designers to partition the design into smaller blocks and provides a precise understanding of the ECO points.
The tool generates the logic patch, along with the integration instructions for the original netlist and the contraints file for the subsequent netlist-to-RTL equivalence checking.
Automatic netlist tracing for accurate ECO points
The patented algorithm automates and simplifies the process of accurately locating the corresponding RTL design function in teh netlist, even if the netlist has undergone the following changes:
Extensive optimization during synthesis
Flattening of hierarchies
Signal names removed
Replication and Instantiation
Cross-hierarchy logic traversals
Insertion of additional logic
Timing and placement dependencies
Generating the smallest possible patch logic
Generating the smallest possible patch logic involves several key steps:
Accurately capture the ECO intent,
Identifying suitable ECO points in the original netlist,
Analyzing the corresponding patch function for each ECO point,
Optimizing the patch logic and path delay intensively.
In many cases, the best ECO change is not at the netlist location where the designer expects it to be.
Complying with original design constraints
All design requirements from the original design will be honored, including repetitively placed changes, feed-through modifications, boundary optimization across hierarchies, ECO operations across clock or power domains (such as managing clock-gating and power isolation cells), and adherence to specific design rules in advanced process nodes like 7nm or 5nm.
Formal verification support
The ECO process generates references for downstream formal verification, allowing users to convert them into constraints for their preferred verification tool. These references include details about ECO netlist mapping and optimization.
Applicable to ECO needs at all phases of ASIC design
The solution is applicable throughout the entire ASIC design cycle, including DFT, P&R, final layout, and even the post-mask scenarios. Tool execution templates provided in the tool package cover all design phases, ensuring seamless applicability.
Effortless plug-and-play integration with the design flow
The tool's easy integration, utilizing standard data interface formats, enables users to incorporate the design flow into their existing tool chains quickly and efficiently.
